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This is needed, due to the fact that the last 12 bits of the 32-bit value are overwritten by access bits and such.

The remaining bits 9 through 11 are not used by the processor, and are free for the OS to store some of its own accounting information.

There is no paging table involved in the address translation.

Note: With 4-Mi B pages, bits 21 through 12 are reserved!

In addition, when P is not set, the processor ignores the rest of the entry and you can use all remaining 31 bits for extra information, like recording where the page has ended up in swap space.

Setting the S bit makes the page directory entry point directly to a 4-Mi B page.

32-bit x86 processors support 32-bit virtual addresses and 4-Gi B virtual address spaces, and current 64-bit processors support 48-bit virtual addressing and 256-Ti B virtual address spaces; and Intel have released documentation for a planned extension to 57-bit virtual addressing and 128-Pi B virtual address spaces.

Note: Only explanations of the bits unique to the page table are below.In fact, current implementations of x86-64 have a limit of between 4 Gi B and 256 Ti B of physical address space (and an architectural limit of 4 Pi B of physical address space).In addition to this, paging introduces the benefit of page-level protection.The page table address field represents the physical address of the page table that manages the four megabytes at that point.Please note that it is very important that this address be 4-Ki B aligned.